Sr. Validation/ FPGA Engineer, System Integration & Debugging Engineer, Sr. FE Design Automation Engineer Jobs @ Intel

Sr. Validation/ FPGA Engineer Qualification:Bachelors or Masters in Electrical Engineering, Computer Engineering or Computer Science. Experience: At the Masters level, a minimum of 4 years of experience with processor and PC system level architectures. System Integration & Debugging Engineer Qualification: BE/ B.Tech./ ME/ M.Tech. Experience: 4 - 6 years of relevant experience. GSM/ UMTS NAS protocol stack Lead Engineer Qualification: Bachelors or Masters degree in Computer Science or Computer Engineering. Experience: 2+ years of software development in wireless protocol stack. Post Graduate Intern Technical Qualification: M.Tech. in VLSI or any Electronics stream. Sr. FE Design Automation Engineer Qualification: Masters in Electronics/ Computer/ Electrical Engineering. Experience: 7+ years of experience in tools, flows and methods used for RTL analysis (Lint, MCP, CDC, low power) and IP qualification/ hand-off. Location: Bangalore For more details, please visit: jobs.intel.com/