Finance Assistant, Verification Engineer, Synthesis/Timing Lead, Software Developer @ Reliable Technosystems India Pvt Ltd

Finance AssistantQualification: B.Com./ M.Com./ CA/ MBA(Fin.). Experience: 2-3 years Skills: Basics of banking, financial transactions & hands on with Tally. Periodic filing of VAT, TDS & Professional tax. Form “C” & other import/export procedure knowledge. Hands on MS Office-Excel, Word. Verification Engineer Qualification: B.Tech./ M.Tech./ MS. Experience: 3+ years Skills: Setting up of verification Tool flow. Hands on Perl/Tcl. Verification Methodology -UVM. Hands on Verilog/ System Verilog. Knowledge of concepts Coverage driven, Assertions & Formal verification. Synthesis/ Timing Lead Qualification: B.Tech./ M.Tech./ MS. Experience: 6+ years Skills: STA expert -Create/update chip level timing constraints. Hands on Synopsys -Prime Time & DC. Scripting in Tcl/Perl for DC/PT. Parsing reports for reports etc. Software DeveloperQualification: B.Tech./ M.Tech./ MS. Experience: 7+ years Skills: SW in Design Verification Environment. Hands on OOP with Perl. Working Knowledge of Unix, Shell, Configuration Management (Perforce). Knowledge of SQL database, EDA tools, Web basics is preferred. How to Apply: Send your Updated resumes to hr@reliabletechsys.com and mention the REQ Code in Subject. Last Date: 20-Aug-2014 For more details, please visit: reliabletechsys.com/hr.html