- ASIC Design Engineer P2Qualifications:Bachelor degree/ Masters degree in Electronics Engineering with good academic record from a reputed institute.
Experience: Minimum of 3 years of experience Synopsys based ICC, and Perl / TCL knowledge is a must.
- ASIC Engineer 1Qualifications: Masters in Engineering/ Bachelors in Engineering from a reputed institute with good academic record.
- Senior Engineer DFTQualifications:
- MSEE or equivalent with 5-8 years experience in ASIC Design for Test design.
- Knowledge of ASIC design and DFT implementation. Memory Bist, Boundary scan, IP Test Power aware DFT implementation Synopsys DFTC Mentor Fast scan ATPG tools, Prime Time for Static Timing Analysis, Formality.
- Must have taped out 40nm or below designs & owned full chip Pattern ATPG, BIST, BSCAN generation and verification & DFT design closure including IP TEST like PLL, DDRPHY, serdes.
- Senior EngineerQualifications:
- MSEE or equivalent with 5-8 years experience in ASIC Physical design.
- Knowledge of ASIC design and implementation. Power aware implementation Synopsys ICC Physical design tools, Prime Time for Static Timing Analysis, Mentor Caliber, Verplex or Formality.
- Must have taped out 40nm or below designs & owned high complexity block timing closure and design closure.
- Staff EngineerQualifications:
- MSEE or equivalent with 8-10 years experience in ASIC Physical design.
- Knowledge of ASIC design and implementation. Power aware implementation Synopsys ICC Physical design tools, Prime Time for Static Timing Analysis, Mentor Caliber, Formality.
- Must have taped out 40nm or below designs & owned full chip SOC timing closure and design closure.
Location: Pune
For more details, please visit: jobs.lsi.com/in/india-jobs
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